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PD - 97354
IRFB4115PBF
HEXFET(R) Power MOSFET
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
G D
D
G S
VDSS RDS(on) typ. max. ID (Silicon Limited)
150V 9.3m 11m 104A
S
TO-220AB
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current c Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery e Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
104 74 420 380 2.5 20 18 -55 to + 175 300 10lbxin (1.1Nxm) 220 See Fig. 14, 15, 22a, 22b
Units
A W W/C V V/ns
C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy d Avalanche Current c Repetitive Avalanche Energy f mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA
Parameter
Junction-to-Case j Case-to-Sink, Flat Greased Surface Junction-to-Ambient ij
Typ.
--- 0.50 ---
Max.
0.40 --- 62
Units
C/W
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1
11/10/08
IRFB4115PBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
Min. Typ. Max. Units
150 --- --- 3.0 --- --- --- --- --- --- 0.18 9.3 --- --- --- --- --- 2.3 --- --- 11 5.0 20 250 100 -100 --- V V/C m V A nA
Conditions
VGS = 0V, ID = 250A Reference to 25C, ID = 3.5mAc VGS = 10V, ID = 62A f VDS = VGS, ID = 250A VDS = 150V, VGS = 0V VDS = 150V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd)
Min. Typ. Max. Units
--- 77 28 26 51 18 73 41 39 5270 490 105 460 530 --- 120 --- --- --- --- --- --- --- --- --- --- --- --- S nC
Conditions
VDS = 50V, ID = 62A ID = 62A VDS = 75V VGS = 10V f ID = 62A, VDS =0V, VGS = 10V VDD = 98V ID = 62A RG = 2.2 VGS = 10V f VGS = 0V VDS = 50V = 1.0 MHz, See Fig. 5 VGS = 0V, VDS = 0V to 120V h, See Fig. 11 VGS = 0V, VDS = 0V to 120V g
97 --- --- --- --- Turn-On Delay Time --- Rise Time --- Turn-Off Delay Time --- Fall Time --- Input Capacitance --- Output Capacitance --- Reverse Transfer Capacitance --- Effective Output Capacitance (Energy Related) --- Effective Output Capacitance (Time Related) ---
ns
pF
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) d Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- 104 420 A A
Conditions
MOSFET symbol showing the G integral reverse p-n junction diode. TJ = 25C, IS = 62A, VGS = 0V f TJ = 25C VR = 130V, TJ = 125C IF = 62A TJ = 25C di/dt = 100A/s f TJ = 125C TJ = 25C
D
S
--- --- 1.3 V --- 86 --- ns --- 110 --- --- 300 --- nC --- 450 --- --- 6.5 --- A Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.11mH RG = 25, IAS = 62A, VGS =10V. Part not recommended for use above this value. ISD 62A, di/dt 1040A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C.
Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994.
2
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IRFB4115PBF
1000
TOP VGS 15V 10V 8.0V 7.0V 6.5V 6.0V 5.5V 5.0V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.5V 6.0V 5.5V 5.0V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
100
BOTTOM
10
5.0V 10
1 5.0V 0.1 0.1 1
60s PULSE WIDTH
Tj = 25C 1 100 0.1 1 10
60s PULSE WIDTH
Tj = 175C 10 100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 62A 2.5
ID, Drain-to-Source Current (A)
VGS = 10V
100
T J = 175C
2.0
10
T J = 25C
1.5
1 VDS = 50V 60s PULSE WIDTH 2 4 6 8 10 12 14 16
1.0
0.1
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
14.0
VGS, Gate-to-Source Voltage (V)
ID= 62A
12.0 10.0 8.0 6.0 4.0 2.0 0.0
10000
C, Capacitance (pF)
Ciss 1000 Coss Crss 100
VDS= 120V VDS= 75V VDS= 30V
10 1 10 100 1000 VDS, Drain-to-Source Voltage (V)
0
20
40
60
80
100
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4115PBF
1000
10000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100
T J = 175C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100sec 100 DC 10msec 10 Tc = 25C Tj = 175C Single Pulse 1 1 10 100 1000 1msec
10 T J = 25C 1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
120 100
ID, Drain Current (A)
Fig 8. Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
VDS, Drain-to-Source Voltage (V)
200 Id = 3.5mA 190 180 170 160 150 140 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C )
80 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
6.0
Fig 10. Drain-to-Source Breakdown Voltage
900
EAS , Single Pulse Avalanche Energy (mJ)
800 700 600 500 400 300 200 100 0
5.0 4.0
Energy (J)
ID TOP 10A 22A BOTTOM 62A
3.0 2.0 1.0 0.0 -20 0 20 40 60 80 100 120 140 160
25
50
75
100
125
150
175
Fig 11. Typical COSS Stored Energy
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRFB4115PBF
1
Thermal Response ( Z thJC ) C/W
D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01
J J 1
R1 R1 2
R2 R2
R3 R3 3 C 3
Ri (C/W) i (sec) 0.0500 0.000052 0.1461 0.2041 0.000468 0.004702
1
2
0.001
SINGLE PULSE ( THERMAL RESPONSE )
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1
0.0001 1E-006
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100 0.01 10 0.05 0.10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
250 TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 62A
EAR , Avalanche Energy (mJ)
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150 Starting T J , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB4115PBF
6.0
VGS(th) , Gate threshold Voltage (V)
50 IF = 42A V R = 130V TJ = 25C TJ = 125C
5.0
40
3.0
ID = 250A ID = 1.0mA ID = 1.0A
IRR (A)
4.0
30
20
2.0
10
1.0 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( C )
0 0 200 400 600 800 1000 diF /dt (A/s)
Fig 16. Threshold Voltage vs. Temperature
50 IF = 62A V R = 130V TJ = 25C TJ = 125C
QRR (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
2500 IF = 42A V R = 130V TJ = 25C TJ = 125C
40
2000
IRR (A)
30
1500
20
1000
10
500
0 0 200 400 600 800 1000 diF /dt (A/s)
0 0 200 400 600 800 1000 diF /dt (A/s)
Fig. 18 - Typical Recovery Current vs. dif/dt
3000 IF = 62A V R = 130V TJ = 25C TJ = 125C
Fig. 19 - Typical Stored Charge vs. dif/dt
2400
QRR (A)
1800
1200
600
0 0 200 400 600 800 1000 diF /dt (A/s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB4115PBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
VDS VGS RG RD
Fig 22b. Unclamped Inductive Waveforms
VDS 90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10% VGS
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit
Current Regulator Same Type as D.U.T.
Fig 23b. Switching Time Waveforms
Id Vds Vgs
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
Vgs(th)
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRFB4115PBF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
(;$03/( 7+,6 ,6 $1 ,5) /27 &2'( $66(0%/(' 21 :: ,1 7+( $66(0%/< /,1( & 1RWH 3 LQ DVVHPEO\ OLQH SRVLWLRQ LQGLFDWHV /HDG )UHH ,17(51$7,21$/ 5(&7,),(5 /2*2 $66(0%/< /27 &2'( 3$57 180%(5
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TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 11/2008
8
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